This invention relates to a process for fabricating a semiconductor integrated circuit and, more particularly, to a process for fabricating a semiconductor integrated circuit whereby a capacitor element may be formed thereon.
There are two kinds of capacitor elements in an integrated circuit. One is referred to as a junction capacitor element. It makes use of a P-N junction. The other is referred to as a metal-oxide semiconductor (MOS) capacitor element. It uses a dielectric substance. The MOS capacitor element has a larger capacitance per unit area than the P-N junction capacitor element.
An example of a MOS capacitor element is disclosed in FIG. 8 of Japanese Laid-open Patent Publication No. 59-28368. A p-type semiconductor substrate 1 is shown with an n-type epitaxial layer 2 and an n.sup.+ -type buried layer 3 therein. P.sup.+ -type isolation regions 4 separate an island region 5 from epitaxial layers 2. Island region 5 is shown sandwiched between buried layer 3 and an n.sup.+ -type first region 6 formed on the surface of island region 5. An oxide film 7 coats the surface of the device. A first electrode 8 and a second electrode 9 form ohmic contacts within n.sup.+ -type first region 6. Dielectric film 10, a very thin oxide film, is formed between first region 6 and second electrode 9 immediately after removing an oxide film 7 completely therefrom. The capacitance between first region 6 and second electrode 9 is the basis of the capacitance within the MOS capacitor element.
Recently, a process for fabricating semiconductor integrated circuits has been developed whereby a bipolar element and a MOS element may be combined forming a bipolar-complementary MOS, hereinafter called Bi-CMOS. However, this process falls short of being able to attach a capacitor element to the Bi-CMOS technology, as mentioned above.